TOP = shift
sim_main = sim_main

verilator:
	#echo "#define Top $(TOP)\n#define VTop V$(TOP)\n#include \"V$(TOP).h\"\n#include \"verilated.h\"\n#include <verilated_vcd_c.h>" > $(sim_main).h
	#verilator -Wall --cc --trace --exe $(TOP).v $(sim_main).cpp
	./build_backup.sh -b -s -t ysyx_210184.v
gtkwave:
	gtkwave.exe ./cpu/build/top.vcd
assemble:
	cd ./cpu/testvector && source makefile
compile:
	make -j 2 -C obj_dir -f V$(TOP).mk V$(TOP)
run:
	echo "Start..."
	./obj_dir/V$(TOP)
clean:
	rm obj_dir/V$(TOP)
cleanall:
	rm -r obj_dir
